1. Field of the Invention
The present invention relates to a process for producing silicide or silicon gates for an integrated circuit having gate-insulator-semiconductor-type elements. It more particularly relates to a novel process making it possible to obtain a very small spacing between gates, which gives integrated circuits, particularly charge transfer devices or circuits using elements of the MOS type (metal - oxide - semiconductor) of a very compact nature.
2. Description of the Prior Art
In the aforementioned circuits, the gates are made from a conductive material, which can e.g. be a metal such as aluminium, a metaloid such as highly doped polycrystalline silicon or formed from a double layer of highly doped polycrystalline silicon covered with a silicide. Photolithography is conventionally used for producing polycrystalline silicon gates or double layer polycrystalline silicon - silicide gates. Thus, according to one of these conventional processes, in order to obtain gates with a double polycrystalline silicon - silicide layer, following the definition of the elements of the circuit by opening windows in a thick insulating layer covering the semiconductor substrate and depositing a thin insulating layer, on the complete circuit is deposited a polycrystalline silicon layer, which is covered with a metal layer giving a silicide. The gates are then defined by masking, irradiation, development and etching. The assembly then undergoes annealing in a neutral atmosphere in order to transform the metallic layer in contact with the polycrystalline silicon into silicide. This process is very simple, but does not make it possible to obtain a spacing between the gates below 2.5 .mu.m.